Design for Test
Custom test architectures that achieve very high test coverage, excellent yield and very low DPPM — a thorough screen for manufacturing defects that is vital to our customers' success.
Test Architecture
Our excellence in devising custom test architecture solutions for a varied set of customers helps us deliver best-in-class SoCs with brilliant yield numbers. We define and develop test RTL and IO mux architecture schemes for both hierarchical monolithic die and chiplet-based multi-die designs.
Test-mode definition
Scan, MBIST, BSCAN, functional-test and debug modes with IO budgeting.
Hierarchical DFT
Core-wrapping, IEEE 1500 and pattern retargeting for large SoCs.
Chiplet & multi-die test
Die-to-die test access, IEEE 1838 and known-good-die strategies.
Test-time & power budgeting
Compression ratios and scan power controls that fit the ATE budget.
DFT Insertion
We take designs through the various DFT stages — boundary scan (BSCAN), memory built-in self-test (MBIST) and scan — using industry-standard EDA tools, and collaborate closely with the back-end team to optimise the result.
What we deliver
- Scan insertion with EDT / DFTMAX compression and OCC
- MBIST with repair (BIRA/BISR) for all memory instances
- LBIST for in-system and automotive safety test
- IEEE 1149.1 / 1149.6 boundary scan and IEEE 1687 (IJTAG) networks
- Test wrappers and IEEE 1500 core-level infrastructure
- DRC-clean, synthesis-ready DFT netlists
ATPG & Pattern Validation
We generate production patterns that hit coverage targets while meeting test-time and power constraints, then validate them in simulation before they reach the tester.
Fault models
Stuck-at, transition, path-delay, bridging and cell-aware ATPG.
Coverage analysis
Untestable-fault root-causing and test-point insertion.
Pattern simulation
Zero-delay and SDF gate-level validation on signoff corners.
Diagnostics
Scan diagnosis and yield-learning support for production ramp.
Test-Mode Constraints & STA
Our test team is self-sufficient in the development and validation of test-mode constraints and closely collaborates with the back-end team to enhance and optimise the design for both functional and test timing.
- Shift, capture and at-speed test-mode SDC
- OCC and clock-chain timing closure
- Test-mode STA and ECO support with PD
- Constraint equivalence and mode-merging checks
ATE & Silicon Support
We translate patterns to ATE formats, support first-silicon bring-up on the tester, and debug pattern mismatches — accurately isolating design issues from test-program or equipment artefacts.
We're hiring DFT engineers
DFT Engineer — scan, MBIST, boundary scan and ATPG on advanced-node SoCs and chiplets.